Many high speed communication systems and networks have employed binary encoding techniques of data to provide a DC-balanced transmission. Serially transmitted binary data that has a preferably zero DC component simplifies design and reliability of transmitter and receiver systems. The so called 8B/10B code is one type of encoding which has become a standard for several high data rate applications. This code is described in an article by Franaszek et al entitled, "A DC-Balanced partitioned-Block, 8B/10B Transmission Code," IBM Journal of Research and Development, Volume 27, 1983, pages 440-451 and U.S. Pat. No. 4,486,739.
In 8B/10B coding, a serial data stream made of 8 bit data packets is encoded to 10 bits of serial transmitted code. The two added bits provide DC balance and enough transitions to assure accurate phase lock loop oscillator clock synchronization as well as other purposes. In fact, 8B/10B coding is usually carried out in two packets, a 5B/6B nibble and 3B/4B nibble. In other words, each D.sub.0 . . . D.sub.7 8 bit byte to be encoded is broken up into 5 bits D.sub.0 . . . D.sub.4 which are encoded into 6 bits and 3 bits, D.sub.5 . . . D.sub.7, which are encoded into 4 bits. The 8B/10B coding scheme is somewhat complex and is best understood by reference to the Tables I and II below given by Franaszek. All the possible 5 bit data values are listed in column labeled "ABCDE" and the corresponding 6 bit code is shown in the column labeled "abcdei."
The term "running disparity" is employed in the prior art as a measure of the DC balance of the encoded data. Specifically, the running disparity is the sum of the disparity of all preceding blocks, where disparity is the difference between the number of zeros and the number of ones in a block. For a given block of 8B/10B coded data, valid code is selected such that the disparity can be either +2, -2 or 0. With reference to Table 1, under column abcdei, note that each code in that column is selected so that the number of ones and zeroes are either equal or differ by an even number. Also, with reference to the column in Table 1 labeled "alternate" and the column labeled "D-1," note that wherever a "+" appears in column D-1, that the number of zeroes exceeds the number of ones by two in the corresponding code in column "abcdei." Also note that for each "+," there appears an entry in the column "ALTERNATE" which is the complement of the binary code in column "abcdei."
The same characteristics are noted for the 3B/4B encoding as shown in the corresponding column labeled "fghi" in Table 2.
One of the features of the 8B/10B codes using the disparity concept described above is that it is convenient to sum the disparity, i.e., +2, 0, or -2, for all bytes while coding the data and if the disparity is positive, then to arrange the logic so that the disparity for the next coded data block to be sent will be negative. For example, to accomplish this, after examining a code block, if the disparity of that block is positive at +2 and the running disparity is positive at +1, then the ALTERNATE code for that block is automatically selected so that the running disparity after the next block is sent will be decremented by -2 so that the running disparity will be negative at -1.
It is also noted that there are codes in Tables 1 and 2 labeled "x" in column D-1 where the number of zeroes and ones are equal. These blocks have disparity equal to "0" and have no ALTERNATE codes because they have no effect on the running disparity.
Circuitry is employed in the receivers of the prior art to verify that the data had been properly encoded, and that no error was introduced in the transmission. Part of this verification is to check that each block complies with the disparity rules, namely, that it is +2, 0, or -2 and that the running disparity is either -1 or +1.
In the prior art receivers, this disparity verification is carried out by combinatorial logic. Because each of the ten bits in the 8B/10B code needs to be evaluated to decode the incoming 10B code, a large number of gates on the order of 100 and a large amount of silicon space were required.
It is the object of this invention to simplify the running disparity verification circuit and to substantially reduce the number of gates and the silicon area required for these functions.